Programmable logic devices (PLDs) are a well-known type of integrated circuit that may be programmed by a user (e.g., a circuit designer) to perform specified logic functions. One type of PLD, the field-programmable gate array (FPGA), can implement thousands of gates of logic on a single integrated circuit. PLDs, including FPGAs, are becoming ever more popular, largely because they require less time to implement than semi-custom and custom integrated circuits.
FIG. 1 (prior art) depicts a conventional FPGA 100. As is typical, FPGA 100 includes an array of configurable logic blocks (CLBs) 105 that are programmably connected to each other and to programmable input/output blocks (IOBs) 110. CLBs 105 include memory arrays that can be configured either as look-up tables (LUTs) that perform specified logic functions or as random-access memory (RAM). Some modern FPGAs also include embedded blocks of RAM 115 optimized for memory applications. Configuration data loaded into internal configuration memory cells (not shown) define the operation of the FPGA by determining how the CLBs, interconnections, block RAM, and IOBs are configured. FPGA 100 may be, for example, a Virtex.TM. FPGA available from Xilinx, Inc., of San Jose, Calif. For a more detailed description of a Virtex.TM. FPGA, see "Virtex.TM.-E 1.8 V Extended Memory Field Programmable Gate Arrays," advance product specification, DS025 (v1.0) Mar. 23, 2000, pages 1-19, which is available from Xilinx, Inc., and is incorporated herein by reference.
FIG. 2 (prior art) depicts another view of FPGA 100 of FIG. 1, like-numbered elements being the same. A majority of CLBs 105 and IOBs 110 are omitted for simplicity. A pair of CLBs 105A and 105B represents two signal sources, each intended to drive a shared signal to a plurality of IOBs 110. Referring first to the left-hand side of FPGA 100, CLB 105A connects to a vertical interconnect line 200 via a buffer 205 and a programmable interconnect point (PIP) 210A. PIP 210A is one of a collection of conventional PIPs used to programmably connect various horizontal and vertical conductors to define desired signal paths. For illustrative purposes, programmed PIPs and the associated signal paths are depicted in FIG. 2 using relatively wide lines.
FPGA 100 is configured such that CLB 105A provides a shared signal S to a series of IOBs 110, the series collectively designated 215. Such configurations are typical when implementing communication channels (e.g., input or output busses) in which a collection of IOBs 110 share common signals, such as clock, clock-enable, write-enable, output-enable, preset and clear signals, to name just a few. In this specification, the IOBs connected to CLB 105A or CLB 105B are designated as "{character pullout}", and the unused IOBs are empty boxes.
The common signal S from CLB 105A traverses different lengths of interconnect lines, depending upon the destination. Consequently, signal S arrives at the various IOBs 110 within series 215 at slightly different times. This difference, conventionally known as "skew," can be a significant problem when attempting to synchronously send or receive relatively fast signals in parallel. For example, it can be very difficult to control a number of IOBs 110 in parallel, as is required to implement a control channel. This problem is exacerbated when the control signal S has both minimum and maximum delay constraints.
In general, the greater the number and separation of signal destinations that must be synchronized, the greater the skew problem. This is particularly true when signals must be routed to IOBs along more than one edge, a situation illustrated on the right-hand side of FIG. 2. In that example, the number of IOBs 110 along the right-hand edge is insufficient to implement a desired synchronous communication channel. Thus, two IOBs 110 from the upper edge of FPGA 100 are joined with a collection of IOBs 110 along the right-hand edge. Unfortunately, wrapping the synchronized signal from signal source 105B around a corner using the conventional interconnect scheme of FIG. 2 exacerbates the skew problem by requiring the inclusion of a group of additional PIPs and interconnect conductors 220. The resulting additional skew can cause FPGA 100 to fail to meet a required timing specification, possibly leading to timing errors. There is therefore a need for improved programmable routing resources capable of distributing low-skew signals along more than one edge of a programmable logic device.